1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a silicide layer on a gate electrode.
2. Description of the Related Art
Silicide layers having reasonably low resistivities are generally used in integrated circuits. Typically, after forming a silicide layer, an annealing step is performed on the silicide layer. The silicide layer rearranges its crystal lattice during the annealing step. The resistivity of the silicide layer thus is further reduced. Therefore, by forming a silicide layer between the interconnections or between the gate and the source/drain region, the resistance between the interconnections or between a gate and a source/drain region can be decreased
Reference is made to FIGS. 1A through 1I, which explain a conventional method of fabricating a silicide layer on a gate electrode.
In FIG. 1A, a shallow trench isolation structure 101 is formed in a semiconductor substrate 100. An active area 103 is next to the shallow trench isolation structure 101. A gate oxide layer 102 and a polysilicon layer 104 are formed in sequence over the semiconductor substrate 100 in the active area 103.
In FIG. 1B, the polysilicon layer 104 is patterned to leave a gate electrode 104a on the gate oxide layer 102.
In FIG. 1C, ion implantation is performed on the substrate 100 with the gate electrode 104a serving as a mask. A lightly doped drain region 106 is formed on opposite sides of the gate electrode 104a in the substrate 100.
In FIG. 1D, a buffer oxide layer 108 is formed over the substrate 100. A silicon nitride (Si.sub.3 N.sub.4) layer 110 is formed on the buffer oxide layer 108.
In FIG. 1E, a portion of the silicon nitride layer 10 and a buffer oxide layer 108 are etched back to form a spacer 110a. The spacer 110a is formed on a sidewall of the gate electrode 104a over the buffer oxide layer 108.
In FIG. 1F, ion implantation is performed with the spacer 110a and the gate electrode 104a serving as masks. A source/drain region 112 is formed on opposite sides of the spacer 110a in the substrate 100.
In FIG. 1G, a potion of the gate oxide layer 102, which is on the source/drain region 112, exposed by the gate electrode 104a and the spacer 110a is removed by wet etching. A metallic layer 113 is formed over the substrate 100 to cover the gate electrode 104a and the spacer 110a.
In FIG. 1H, a thermal step is performed. The metallic layer 113 in contact with the gate electrode 104a and the source/drain region 112 are transformed into a silicide layer 114.
In FIG. 1I, the remaining metallic layer 113, which does not react during the thermal step, is removed.
However as seen in the above description, the silicide layer 114 is formed only on the top surface of the gate electrode 104a. The gate resistance that the silicide layer 114 can decrease is limited. Thus, the gate has a high resistance, which reduces the performance speed of devices.